Test circuit and method
US11768235B2 · kind B2 · utility
1Cited by
2References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 9, 2023 |
| Grant date | Sep 26, 2023 |
| Priority date | — |
| Expiry date | Jan 9, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/2879
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
An IC includes a plurality of pads at a top surface of a semiconductor wafer, an amplifier configured to receive a first AC signal at an input terminal, and output a second AC signal at an output terminal, a first detection circuit coupled to the input terminal and configured to output a first DC voltage to a first pad of the plurality of pads responsive to the first AC signal, and a second detection circuit coupled to the output terminal and configured to output a second DC voltage to a second pad of the plurality of pads responsive to the second AC signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.