Interface between processing unit and an external nonvolatile memory
US11768794B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 22, 2022 |
| Grant date | Sep 26, 2023 |
| Priority date | — |
| Expiry date | Mar 22, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F1/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An interface between two devices is disclosed. To consume power, the signals used in the interface utilize CMOS signalling. Further, to achieve high speed, a reduced frequency clock is transmitted from one device to the second device. The second device has a clock multiplier to recreate the original clock. Both devices utilize a clock phase alignment block which aligns the phase of the clock with the incoming data. The clock phase alignment block utilizes a digital PLL to consume power. Further, since the digital PLL retains its state, the reduced frequency clock may be disabled when data is not being transmitted. This interface may be used to transmit serial data at rates up to and exceeding 2.5 Gbits/sec.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.