Semiconductor chip and semiconductor package including the same
US11769742B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 18, 2022 |
| Grant date | Sep 26, 2023 |
| Priority date | — |
| Expiry date | May 18, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2224/2919
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Disclosed embodiments include a semiconductor chip including a semiconductor substrate having a top surface with a top connection pad disposed therein, and a protection insulation layer comprising an opening therein, the protection insulation layer not covering at least a portion of the top connection pad, on the semiconductor substrate. The protection insulation layer may include: a bottom protection insulation layer, a cover insulation layer comprising a side cover part that covers at least a portion of a side surface of the bottom protection insulation layer and a top cover part disposed apart from the side cover part to cover at least a portion of a top surface of the bottom protection insulation layer. The protection insulation layer may further include a top protection insulation layer on the top cover part.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.