Process for collectively curving a set of electronic chips
US11769785B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 16, 2020 |
| Grant date | Sep 26, 2023 |
| Priority date | — |
| Expiry date | Jan 13, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10F39/811
Abstract
A process includes providing electronic chips, the chips having been diced beforehand and each including a stack including a matrix-array of pixels, an interconnect layer, first layer, joining the electronic chips to a carrier substrate, so as to leave a spacing region between the chips; forming a redistribution layer having lateral ends extending into each spacing region; forming metal pillars on the lateral ends; moulding a material including first segments, facing the first layers, second segments which are separate from the first segments, and which extend around the metal pillars; the first and second segments being coplanar; applying a heat treatment, the formed material being chosen so that the stack is curved with a convex shape; the second segments remaining coplanar at the end.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.