Dynamic enhancement of loop response upon recovery from fault conditions
US11770071B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 17, 2021 |
| Grant date | Sep 26, 2023 |
| Priority date | — |
| Expiry date | Jun 17, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K7/08
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
A method for dynamic enhancement of loop response upon recovery from fault conditions includes detecting a fault condition in response to a programmed output voltage of a Pulse Width Modulation (PWM) converter decreasing below an input voltage of the PWM converter. A peak voltage is sampled at the end of at least one of a plurality of clock cycles of the PWM converter in response to detecting the fault condition, wherein the peak voltage is proportional to a sensed current conducted through a transistor. An error output of an error amplifier is preset to an error value determined by the peak voltage. A PWM driver is controlled with the error value to drive the transistor. An output load is charged to the programmed output voltage with the transistor in response to the input voltage increasing above the programmed output voltage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.