Semiconductor device with trench structure to reduce parasitic capacitance and leakage current
US11770925B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 4, 2021 |
| Grant date | Sep 26, 2023 |
| Priority date | — |
| Expiry date | Jun 4, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/485
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device includes a semiconductor substrate including a trench, a direct contact in the trench, the direct contact having a width smaller than a width of the trench, a bit line structure on the direct contact, the bit line structure having a width smaller than the width of the trench, a first spacer including a first portion and a second portion, the first portion extending along an entire side surface of the direct contact, and the second portion extending along the trench, a second spacer on the first spacer, the second spacer filling the trench, a third spacer on the second spacer, and an air spacer on the third spacer, the air spacer being spaced apart from the second spacer by the third spacer, wherein the first spacer includes silicon oxide.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.