Vertical memory devices with segmented charge storage layers
US11770929B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 14, 2020 |
| Grant date | Sep 26, 2023 |
| Priority date | — |
| Expiry date | Mar 2, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/037
Abstract
A semiconductor device includes gate layers stacked on a substrate in a first direction perpendicular to an upper surface of the substrate, and channel structures penetrating the gate layers and extending in the first direction, each of the channel structures includes first dielectric layers on side surfaces of the gate layers, respectively, and spaced apart from each other in the first direction, electric charge storage layers on side surfaces of the first dielectric layers, respectively, and spaced apart from each other in the first direction, a second dielectric layer extending perpendicularly to the substrate to conform to side surfaces of the electric change storage layers, and a channel layer extending perpendicularly, and each of the first dielectric layers has a first maximum length, and each of the electric charge storage layers has a second maximum length greater than the first maximum length in the first direction.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.