Integrity tree for memory integrity checking
US11775177B2 · kind B2 · utility
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19Claims
0Family size
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Key dates
| Filing date | Oct 17, 2019 |
| Grant date | Oct 3, 2023 |
| Priority date | — |
| Expiry date | Oct 17, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F21/64
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus (4) comprises memory access circuitry (12) to control access to data stored in a memory; and memory integrity checking circuitry (20) to verify integrity of data stored in the memory, using an integrity tree (26) in which the association between parent and child nodes is provided by a pointer. This helps to reduce the memory footprint of the tree.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.