Maintaining synchronisation between memory writing and reading blocks using an internal buffer and a control channel
US11775206B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 2, 2021 |
| Grant date | Oct 3, 2023 |
| Priority date | — |
| Expiry date | Jul 17, 2041 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A hardware unit for manipulating data stored in a memory comprises an internal buffer, a memory reading block, configured to read the data from the memory and write the data to the internal buffer. a memory writing block, configured to read the data from the internal buffer and write the data to the memory. The hardware unit optionally also comprises a control channel between the memory reading block and the memory writing block, wherein the memory reading block and the memory writing block are configured to communicate via the control channel to maintain synchronisation between them when writing the data to the internal buffer and reading the data from the internal buffer, respectively. The hardware unit may be configured to apply one or more transformations to multidimensional data in the memory. The hardware unit may be configured to traverse the multidimensional array using a plurality of nested loops.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.