Computing system for reducing latency between serially connected electronic devices
US11775451B2 · kind B2 · utility
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5References
9Claims
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Key dates
| Filing date | May 26, 2022 |
| Grant date | Oct 3, 2023 |
| Priority date | — |
| Expiry date | May 26, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2213/0026
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A computing system includes a host, a first electronic device connected to the host, and a second electronic device that communicates with the host through the first electronic device. The first electronic device requests a command written in a submission queue of the host based on a doorbell transmitted from the host, stores the command transmitted from the host, requests write data stored in a data buffer of the host, and stores the write data of the data buffer transmitted from the host.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.