Autonomous detection of cache-based side-channel attacks
US11775635B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 23, 2020 |
| Grant date | Oct 3, 2023 |
| Priority date | — |
| Expiry date | Apr 20, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06N20/20
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for detecting a cache-based side-channel attack includes utilizing a timer thread that continuously increments a variable in code of an application. The code has been instrumented such that the instrumented code uses the variable incremented by the timer thread to infer an amount of time taken for running a part of the code. A number of cache misses during execution of the part of the code is determined based on the amount of time. It is determined whether the application is experiencing the cache-based side-channel attack using a classifier which uses as input the number of cache misses.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.