System and method for supporting multiple independent silicon-rooted trusts per system-on-a-chip
US11775690B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 2, 2020 |
| Grant date | Oct 3, 2023 |
| Priority date | — |
| Expiry date | Nov 19, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2221/033
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A compute device of an information handling system includes a security chip. The security chip includes a programmable read only memory, which in turn includes multiple one-time programmable slots and a one-time programmable slot counter. A first slot of the one-time programmable slots stores a first group of keys associated with a first entity of the security chip. A second slot of the one-time programmable slots stores a second group of keys associated with a second entity of the security chip. The one-time programmable slot counter includes multiple entries. Each of the entries is associated with a different one of the one-time programmable slots. Each of the entries is preset to a first value. The one-time programmable slot counter is only able to count in one direction. A first entry of the entries is updated to invalidate the second group of keys associated with the second entity.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.