Integrated circuit development using machine learning-based prediction of power, performance, and area
US11775720B2 · kind B2 · utility
1Cited by
9References
20Claims
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Key dates
| Filing date | Jul 2, 2021 |
| Grant date | Oct 3, 2023 |
| Priority date | — |
| Expiry date | Jan 27, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06N20/20
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Aspects of the invention include obtaining one or more feature values that define an architecture design of a memory array and implementing a machine learning model to obtain a predicted power, performance, and area (PPA) of the memory array based on the one or more features. The predicted PPA output by the machine leaning model is assessed based on predefined PPA goals. A design of an integrated circuit that includes the memory array is finalized and fabricated based on the predicted PPA meeting the predefined PPA goals.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.