Systems and methods for obfuscating a circuit design
US11775722B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 4, 2021 |
| Grant date | Oct 3, 2023 |
| Priority date | — |
| Expiry date | Dec 25, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2119/18
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Systems and methods for generating an integrated circuit (IC) chip design are described. One of the methods includes receiving, on a data sheet, by a server, electrical parameters of a system on chip (SoC) to be designed. The method further includes receiving physical parameters of the SoC on the data sheet, generating a first design of the SoC according to the electrical parameters and the physical parameters, and receiving test parameters for testing the first design. The method further includes testing, via a design verification tool, the first design by applying the test parameters to the first design, receiving a second design of a second SoC, and coupling the second design to the first design to generate a first IC chip design. The method includes arranging the first IC chip design to be included on a shuttle for fabricating a first IC chip.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.