Methods, systems, and computer program products for efficiently implementing a 3D-IC
US11775723B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 30, 2021 |
| Grant date | Oct 3, 2023 |
| Priority date | — |
| Expiry date | Jun 30, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/396
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Disclosed is an improved approach for efficiently implementing a three-dimensional integrated circuit (3D-IC) design with heterogeneous and/or homogeneous dies. A first die design and a second die design in a three-dimensional (3D) electronic design maybe identified, and a wrapper design may be generated for at least a block of circuit component designs in the second die design for concurrent implementation of both the first and the second die designs. Both the first and the second dies of the 3D electronic design are concurrently implemented based at least upon a floorplan that is generated with at least the wrapper design for the 3D electronic design. A first wrapper and a second wrapper may be respectively generated for the first die design and the second die design based at least in part upon a result of the concurrent implementation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.