Scheduling heterogeneous execution on heterogeneous hardware
US11775811B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 8, 2019 |
| Grant date | Oct 3, 2023 |
| Priority date | — |
| Expiry date | Mar 29, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2209/484
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The subject technology determines input parameters and an output format of algorithms for a particular functionality provided by an electronic device. The subject technology determines an order of the algorithms for performing the particular functionality based on temporal dependencies of the algorithms, and the input parameters and the output format of the algorithms. The subject technology generates a graph based on the order of the algorithms, the graph comprising a set of nodes corresponding to the algorithms, each node indicating a particular processor of the electronic device for executing an algorithm. Further, the subject technology executes the particular functionality based on performing a traversal of the graph, the traversal comprising a topological traversal of the set of nodes and the traversal being based on a score indicating whether selection of a particular node for execution over another node enables a greater number of processors to be utilized at a time.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.