Method for generating an memory built-in self-test algorithm circuit
US11776649B2 · kind B2 · utility
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Key dates
| Filing date | Apr 11, 2022 |
| Grant date | Oct 3, 2023 |
| Priority date | — |
| Expiry date | Apr 11, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/3602
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for generating a memory built-in self-test circuit includes steps of providing an editable file, wherein the editable file configured to be edited by a user to customize a memory test algorithm; performing a syntax parsing on the editable file to obtain the memory test data, wherein the memory test data being corresponding to the memory test algorithm; and generating the memory built-in self-test circuit based on the memory test data.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.