Semiconductor device
US11776857B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 3, 2022 |
| Grant date | Oct 3, 2023 |
| Priority date | — |
| Expiry date | Jan 3, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/0188
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for manufacturing a semiconductor device includes forming a first active fin and a second active fin on a first active region and a second active region of a substrate, respectively, forming a device isolation layer to cover sidewalls of lower portions of the first active fin and the second active fin, forming a first liner layer and a second liner layer to cover upper portions of the first active fin and the second active fin, respectively, forming a first gate electrode and a second gate electrode on the first active fin and the second active fin, respectively, and forming a first source/drain region and a second source/drain region on the first active fin and the second active fin, respectively. The first liner layer includes a different material from a material of the second liner layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.