Semiconductor package having stiffening structure
US11776918B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 28, 2022 |
| Grant date | Oct 3, 2023 |
| Priority date | — |
| Expiry date | Mar 28, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3511
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor package having a stiffening structure is disclosed. The semiconductor package includes a substrate, an interposer on the substrate, and a first logic chip, a second logic chip, memory stacks and stiffening chips, all of which are on the interposer. The first logic chip and the second logic chip are adjacent to each other. Each memory stack is adjacent to a corresponding one of the first logic chip and the second logic chip. Each memory stack includes a plurality of stacked memory chips. Each stiffening chip is disposed between corresponding ones of the memory stacks, to be aligned and overlap with a boundary area between the first logic chip and the second logic chip.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.