Efficiency concept for driving a PMOS and NMOS full-bridge power stage
US11777497B1 · kind B1 · utility
0Cited by
2References
8Claims
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Assignee
Inventor
Key dates
| Filing date | Mar 29, 2022 |
| Grant date | Oct 3, 2023 |
| Priority date | — |
| Expiry date | Mar 29, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K2217/0072
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
A circuit, which might be a full-bridge driver circuit, comprises a first PMOS high-side transistor device and a first NMOS low-side transistor device. The circuit further comprises turn-on circuitry configured to turn on the first PMOS high-side transistor device while simultaneously turning on the first NMOS low-side transistor device, by routing charge stored in a gate of the first PMOS high-side transistor device to a gate of the first NMOS low-side transistor device, to charge the gate of the first NMOS low-side transistor device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.