Patent · US Active

FDAC/2 spur estimation and correction

US11777513B2 · kind B2 · utility

0Cited by
2References
20Claims
0Family size

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Inventors

Key dates

Filing dateNov 30, 2021
Grant dateOct 3, 2023
Priority date
Expiry dateNov 30, 2041

Classification

  • Technology area (CPC H)Electricity
  • CPC primaryH03M1/662
  • WIPO fieldBasic communication processes
  • WIPO sectorElectrical engineering

Abstract

A spur correction system for a transmit chain having an interleaving multiplexer. In some embodiments, the spur correction system includes a spur sense chain, a correction controller, and a Q path corrector. The interleaving multiplexer combines signals from multiple bands in response to a clock signal. The spur sense chain estimates an error that is in phase with the clock signal (an I-phase error) and an error that is a derivative of the clock signal (a Q-phase error). The correction controller compensates for the estimated I-phase error by injecting an I-phase correction signal into the transmit chain. The Q path corrector compensates for the estimated Q-phase error by selectively connecting one or more capacitors within the interleaving multiplexer.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.