Ic with graphene fet sensor array patterned in layers above circuitry formed in a silicon based cmos wafer
US11782057B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 17, 2021 |
| Grant date | Oct 10, 2023 |
| Priority date | — |
| Expiry date | Mar 6, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01N27/4146
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
An integrated circuit (IC) chip includes ROIC circuitry in a CMOS wafer with a top dielectric layer and at least one graphene field effect transistor (gFET) sensor array added above the CMOS wafer. The IC chip includes access transistors controlled by the ROIC circuitry and further includes sensing circuitry which includes the at least one gFET sensor array and a passivation opening that allows direct contact of a sample liquid with the graphene channels of the gFETs in the at least one gFET sensor array, such that a liquid gate is formed above the graphene channel upon receipt of the sample liquid. In some examples, the IC chip includes a process, memory controller, and memory. A system and a method have similar structures and perform the functions of the apparatus.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.