Time to digital conversion
US11782393B2 · kind B2 · utility
Inventors
Key dates
| Filing date | Jun 2, 2021 |
| Grant date | Oct 10, 2023 |
| Priority date | — |
| Expiry date | Jun 2, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K2005/00078
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Time-to-digital converter (TDC) using multiple Vernier in a cascaded architecture reduces the timing jitter by decreasing the number of the ring oscillator cycles during the measurement processes. Time-to-digital converter (TDC) measurements using a third oscillator for the second Vernier process has significant advantages compared to changing the period of the second oscillator during the measurement cycle. The Vernier architecture described herein may operate with faster oscillators, reducing the number of intervals before converging and leading to a lower time conversion and a better timing jitter Adding multiple cascaded Vernier interpolation may further improve the TDC measurement resolution while having only a small increment of time required to resolve the time interval calculations.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.