Gate driver for separately charging a node voltage of buffers and display device including the same
US11783780B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 22, 2021 |
| Grant date | Oct 10, 2023 |
| Priority date | — |
| Expiry date | Dec 22, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG09G2330/12
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
Proposed is a gate driver and a display device having the same. The gate driver includes a plurality of stage circuits, wherein each of the plurality of stage circuits includes a shift register configured to control charging and discharging of a Q node and a QB node, and a plurality of output buffers sequentially connected to the shift register, wherein each of the output buffers includes a first transistor configured to transmit a voltage of the Q node to a Q′ node, a pull-up transistor configured to output a clock signal to a gate line in response to a voltage of the Q′ node, and a pull-down transistor configured to output a low-potential voltage to the gate line in response to a voltage of the QB node.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.