Display panel and display device
US11783793B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 26, 2022 |
| Grant date | Oct 10, 2023 |
| Priority date | — |
| Expiry date | Oct 26, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG09G2320/0247
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A display panel includes data lines and scanning lines in a display region, and a demultiplexer in a non-display region. The demultiplexer includes m branches. m is an integer. m≥2. Each branch includes a switching transistor which includes a first electrode coupled with an input terminal of the demultiplexer, a second electrode coupled with one of the data lines, and a control electrode for receiving a switching control signal. The demultiplexer includes a first demultiplexer including a compensation transistor, of which first and second electrodes are short-circuited. The compensation transistor is coupled with the data line and has a control electrode for receiving a compensation control signal. The compensation control signal received by the compensation transistor in the branch has one functional rising edge in a period during which the scanning line provides an effective level signal once.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.