Method of forming electronic chip package having a conductive layer between a chip and a support
US11784104B2 · kind B2 · utility
0Cited by
4References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 30, 2021 |
| Grant date | Oct 10, 2023 |
| Priority date | — |
| Expiry date | Dec 24, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2224/95
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The invention concerns a device comprising a support, an electrically-conductive layer covering the support, a semiconductor substrate on the conductive layer, and an insulating casing.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.