Integrated chip inductor structure
US11784211B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 27, 2020 |
| Grant date | Oct 10, 2023 |
| Priority date | — |
| Expiry date | Sep 10, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01F2017/0086
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
The present disclosure relates to, in part, an inductor structure that includes an etch stop layer arranged over an interconnect structure overlying a substrate. A magnetic structure includes a plurality of stacked layers is arranged over the etch stop layer. The magnetic structure includes a bottommost layer that is wider than a topmost layer. A first conductive wire and a second conductive wire extend in parallel over the magnetic structure. The magnetic structure is configured to modify magnetic fields generated by the first and second conductive wires. A pattern enhancement layer is arranged between the bottommost layer of the magnetic structure and the etch stop layer. The pattern enhancement layer has a first thickness, and the bottommost layer of the magnetic structure has a second thickness that is less than the first thickness.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.