Method of manufacturing a III-V based optoelectronic device
US11784456B2 · kind B2 · utility
Inventor
Key dates
| Filing date | Aug 25, 2020 |
| Grant date | Oct 10, 2023 |
| Priority date | — |
| Expiry date | Apr 4, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10H20/0133
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
A method of manufacturing a III-V based optoelectronic device on a silicon-on-insulator wafer. The silicon-on-insulator wafer comprises a silicon device layer, a substrate, and an insulator layer between the substrate and silicon device layer. The method includes the steps of: providing a device coupon, the device coupon being formed of a plurality of III-V based layers; providing the silicon-on-insulator wafer, the wafer including a cavity with a bonding region; transfer printing the device coupon into the cavity, and bonding a layer of the device coupon to the bonding region, such that a channel is left around one or more lateral sides of the device coupon; filling the channel with a bridge-waveguide material; and performing one or more etching steps on the device coupon, silicon-on-insulator wafer, and/or channel.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.