System-latency-aware display device
US11784906B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 4, 2020 |
| Grant date | Oct 10, 2023 |
| Priority date | — |
| Expiry date | Jun 4, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG09G2354/00
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A display device for measuring the end-to-end latency of a computing system. The computing system includes an input device, a computing device, and the display device. The display device is directly connected with the input device and receives input data packets generated by the input device in response to received user input events. The display device passes the input packets to the computing device for graphics processing. The display device measures the end-to-end latency comprising the sum of three latencies. A first latency comprises an input delay of the input device. A second latency comprises an amount of time between generation of the input packet and a corresponding change in pixel values caused by the input event at the display device. A third latency comprises a display latency. The display device also displays latency information associated with the measured end-to-end latency.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.