Array substrate comprising an interlay insulation layer including at least two inorganic insulation layers and at least one organic insulation layer laminated one on another
US11785811B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Apr 27, 2021 |
| Grant date | Oct 10, 2023 |
| Priority date | — |
| Expiry date | Aug 21, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10K59/1201
Abstract
An array substrate, a method for manufacturing the array substrate and a display device are provided. The array substrate includes: a base substrate, and a thin film transistor, a storage capacitor, and a lapping pattern for connecting the thin film transistor to the storage capacitor arranged on the base substrate; wherein the thin film transistor includes a semiconductor layer, a gate insulation layer, a gate electrode, an interlayer insulation layer, a source electrode and a drain electrode arranged sequentially in that order; the interlayer insulation layer includes at least two inorganic insulation layers and at least one organic insulation layer laminated one on another, and both a layer proximate to the base substrate and a layer distal to the base substrate in the interlayer insulation layer are the inorganic insulation layers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.