Three-dimentional packaging method and package structure of photonic-electronic chip
US11789218B2 · kind B2 · utility
4Cited by
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38Claims
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Key dates
| Filing date | Apr 28, 2022 |
| Grant date | Oct 17, 2023 |
| Priority date | — |
| Expiry date | Apr 28, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2224/81986
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present disclosure provides a three-dimensional packaging method and a three-dimensional package structure of a photonic-electronic chip. The method includes: fixing an electronic chip on a first area of a first surface of a photonic chip; fixing a dummy chip on a second area of the first surface of the photonic chip, wherein the photonic chip is provided with an optical coupling interface at the second area, and the dummy chip has a cavity with a single-sided opening, and the opening of the cavity faces and covers an optical coupling interface.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.