Data process apparatus for to-be-cached matrix and method thereof
US11790592B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 15, 2022 |
| Grant date | Oct 17, 2023 |
| Priority date | — |
| Expiry date | Apr 24, 2042 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present disclosure relates to a data process apparatus and a method thereof. The data process apparatus includes an internal memory unit and a shader level-1 cache. The internal memory unit is configured to store a to-be-cached matrix. The to-be-cached matrix includes at least a first element and a second element. The first element and the second element are stored in the internal memory unit in order of elements. The first element is located in a first row of the to-be-cached matrix, and the second element is located in next row of the to-be-cached matrix adjacent to the first row. The shader level-1 cache is connected to the internal memory unit, and configured to acquire the to-be-cached matrix to obtain a to-be-processed matrix stored in order of elements, and store the to-be-processed matrix. The data process apparatus can improve the efficiency of accessing the internal memory unit and reduce the bandwidth occupied by invalid data; enable hardware pipelines to be tighter and reduce idle clock cycles; and enable the shader level-1 cache to be smaller, thereby reducing hardware costs.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.