Shift register and driving method thereof, drive circuit and display device
US11790826B2 · kind B2 · utility
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1References
14Claims
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Key dates
| Filing date | Dec 29, 2020 |
| Grant date | Oct 17, 2023 |
| Priority date | — |
| Expiry date | Aug 26, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG09G2330/06
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
Provided are a shift register and a driving method thereof, a drive circuit and a display device. A first capacitor is provided with a first terminal electrically connected to a cascade signal output terminal and a second terminal electrically connected to a fixed voltage signal terminal, so that a load capacitance of the cascade signal output terminal is compensated, and the charging and discharging process of the first capacitor is combined to reduce a noise of a signal of the cascade signal output terminal and improve the signal stability of the cascade signal output terminal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.