Manufacturing method of semiconductor structure and semiconductor structure
US11791163B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Jun 19, 2022 |
| Grant date | Oct 17, 2023 |
| Priority date | — |
| Expiry date | Jun 19, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/482
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A manufacturing method of a semiconductor structure includes: providing a target layer; forming a plurality of first mask patterns on a top surface of the target layer; forming a plurality of second mask patterns above the target layer, where each of the second mask patterns covers at least a part of a top surface of each of the first mask patterns and a part of the top surface of the target layer in an extension direction of the second mask pattern; performing a first etching on the target layer based on the second mask patterns; removing the second mask patterns; and performing a second etching on the target layer based on the first mask patterns.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.