Clock recovery circuit for display
US11791826B2 · kind B2 · utility
0Cited by
4References
17Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 2, 2022 |
| Grant date | Oct 17, 2023 |
| Priority date | — |
| Expiry date | Dec 2, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/093
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
The present disclosure discloses a clock recovery circuit for a display, which recovers a clock from a clock data signal. The clock recovery circuit includes a clock recoverer configured to generate delayed clocks using a multi-stage delay chain including delay units; and a delay compensator configured to control a first delay time of a first delay unit to be the same as a second delay time of remaining delay units. The clock recovery circuit may compensate for a difference in delay time between the first delay time and the second delay time.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.