ADC apparatus and control method
US11791830B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 7, 2022 |
| Grant date | Oct 17, 2023 |
| Priority date | — |
| Expiry date | Dec 7, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/46
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An apparatus includes a plurality of binary weighted capacitors coupled between a first input terminal of a comparator and a plurality of signal buses, wherein the plurality of binary weighted capacitors has a binary weight increasing by two times from a first capacitor to an (N−K)th capacitor, and a constant binary weight from the (N−K)th capacitor to a (N−K−2+2(K+1))th capacitor, an offset voltage generator configured to generate a digitally controlled offset voltage having 2(K+1) steps fed into a second input terminal of the comparator, and a successive approximation logic block configured to receive an output signal of the comparator, and generate an N-bit control signal for controlling the plurality of binary weighted capacitors.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.