Memory device having a plurality of low power states
US11797203B2 · kind B2 · utility
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Key dates
| Filing date | Sep 6, 2022 |
| Grant date | Oct 24, 2023 |
| Priority date | — |
| Expiry date | Sep 6, 2042 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and memory device of controlling a plurality of low power states are provided. The method includes: entering a low power mode state, in which memory cell rows of the memory device are refreshed and power consumption is lower than in a self-refresh mode state, in response to a low power state entry command; and exiting the low power mode state based on a low power mode exit latency time that is set in a mode register of the memory device or at least one of an alarm signal and a low power mode exit command.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.