System and method for managing faults in integrated circuits
US11797373B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 13, 2021 |
| Grant date | Oct 24, 2023 |
| Priority date | — |
| Expiry date | Apr 22, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/079
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An integrated circuit includes a functional circuit, a detection circuit, a processing circuit, and a recovery circuit. The detection circuit detects a fault in the functional circuit and generates a fault indication indicative of the detected fault. The processing circuit receives the fault indication and identifies a functional domain identifier (ID) associated with the fault. Based on the fault indication, the processing circuit generates context tag data that is indicative of a type of the fault and an operational state of the functional circuit when the fault is detected therein. Further, the processing circuit assigns a priority level to the fault based on the context tag data and the functional domain ID. The recovery circuit performs, based on the functional domain ID, the context tag data, and the first priority level, a recovery operation to recover the functional circuit from the fault.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.