Electronic device, system-on-chip, and operating method thereof
US11797450B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 16, 2021 |
| Grant date | Oct 24, 2023 |
| Priority date | — |
| Expiry date | Jun 23, 2041 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An electronic device includes a cache memory including a memory space for storing a first cache set including a plurality of sector data and a plurality of dirty bits, each of the plurality of dirty bits representing whether corresponding sector data of the plurality of sector data are modified, a memory controller, connected to a plurality of data lines and a data mask line, for receiving the plurality of sector data and the plurality of dirty bits from the cache memory, setting a logic level of a data mask signal based on a logic level of each of the plurality of dirty bits, and outputting the plurality of sector data through the plurality of data lines and the data mask signal through the data mask line, and a memory device, connected to the plurality of data lines and the data mask line, for receiving the plurality of sector data through the plurality of data lines, and receiving the data mask signal through the data mask line.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.