Non-volatile storage system with hybrid SLC wear leveling
US11798643B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Mar 15, 2022 |
| Grant date | Oct 24, 2023 |
| Priority date | — |
| Expiry date | Jul 14, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B43/27
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Technology is disclosed herein for reducing wear due to erasing and programming non-volatile memory cells. The memory system selects a hybrid SLC group of cells for programming to an SLC mode while the selected hybrid SLC group is presently programmed to either the SLC mode or an MLC mode. Memory cells in the selected hybrid SLC group are erased to an SLC erased state regardless of the presently programmed mode of the selected hybrid SLC group. An average memory cell Vt of the SLC erased state is greater than an average threshold voltage of an MLC erased state. Memory cells in the selected hybrid SLC group are programmed from the SLC erased state to an SLC programmed state. Erasing the hybrid SLC group to the SLC erased state reduces wear relative to erasing to the MLC erased state. Therefore, the useful life of the hybrid SLC group is extended.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.