Semiconductor isolation structure and method of making the same
US11798836B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 17, 2021 |
| Grant date | Oct 24, 2023 |
| Priority date | — |
| Expiry date | Nov 11, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L23/535
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor isolation structure includes a silicon-on-insulator wafer, a first deep trench isolation structure and a second deep trench isolation structure. The silicon-on-insulator wafer includes a semiconductor substrate, a buried insulation layer disposed on the semiconductor substrate, and a semiconductor layer disposed on the buried insulation layer. The semiconductor layer has a functional region. The first deep trench isolation structure penetrates the semiconductor layer and the buried insulation layer, and surrounds the functional region. The second deep trench isolation structure penetrates semiconductor layer and the buried insulation layer, and surrounds the first deep trench isolation structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.