Semiconductor package with plurality of grooves on lower surface
US11798869B2 · kind B2 · utility
0Cited by
6References
8Claims
0Family size
Assignee
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Key dates
| Filing date | Aug 16, 2021 |
| Grant date | Oct 24, 2023 |
| Priority date | — |
| Expiry date | Jan 18, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/181
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor package includes: a plurality of die pads; a plurality of semiconductor chips provided on the plurality of die pads respectively; a plurality of lead terminals connected to the plurality of semiconductor chips respectively; and a package sealing the plurality of die pads, the plurality of semiconductor chips, and the plurality of lead terminals, the plurality of die pads and the plurality of lead terminals are exposed from a lower surface of the package, and on the lower surface of the package, grooves are provided among the die pads adjacent to one another and among the lead terminals adjacent to one another.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.