Semiconductor devices having standard cells therein with improved integration and reliability
US11798933B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 13, 2021 |
| Grant date | Oct 24, 2023 |
| Priority date | — |
| Expiry date | Jan 22, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/853
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device includes first and second standard cells having respective semiconductor elements and first interconnection lines electrically connected to the semiconductor elements, on a substrate. A routing structure is provided, which is disposed on the first and second standard cells. The routing structure includes second interconnection lines electrically connected to the first interconnection lines. The first interconnection lines include a first power transmission line, which is configured to supply power to a semiconductor element, and a first signal transmission line electrically coupled to a semiconductor element. The second interconnection lines include: (i) a second power transmission line electrically connected to the first power transmission line and extending by a first length, (ii) a second signal transmission line electrically connected to the first signal transmission line, and (iii) a staple line electrically connected to the first power transmission line, extending on a boundary between the first and second standard cells, and extending by a second length, less than the first length.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.