Transistor source/drain contacts and methods of forming the same
US11798943B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 4, 2021 |
| Grant date | Oct 24, 2023 |
| Priority date | — |
| Expiry date | Jul 20, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/797
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
In an embodiment, a method includes: depositing a protective layer on a source/drain region and a gate mask, the gate mask disposed on a gate structure, the gate structure disposed on a channel region of a substrate, the channel region adjoining the source/drain region; etching an opening through the protective layer, the opening exposing the source/drain region; depositing a metal in the opening and on the protective layer; annealing the metal to form a metal-semiconductor alloy region on the source/drain region; and removing residue of the metal from the opening with a cleaning process, the protective layer covering the gate mask during the cleaning process.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.