Array substrate, display panel and large glass panel
US11798957B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 29, 2021 |
| Grant date | Oct 24, 2023 |
| Priority date | — |
| Expiry date | Jun 11, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/441
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
The present disclosure relates to an array substrate, a display panel, and a large glass panel. The array substrate includes a test structure. The test structure includes a substrate, and a first conductive layer, an insulating layer, a second conductive layer, and a passivation layer sequentially stacked on the substrate. The passivation layer is provided with at least one first groove, at least one second groove, and one third groove. An opening size of the third groove is greater than opening sizes of the at least one first groove and the at least one second groove. The first groove penetrates through the passivation layer and extends to the first conductive layer. The second groove penetrates through the passivation layer and extends to the second conductive layer. The third groove penetrates through the passivation layer and extends to the first conductive layer or the second conductive layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.