Flip flop circuit
US11799458B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 11, 2022 |
| Grant date | Oct 24, 2023 |
| Priority date | — |
| Expiry date | Mar 11, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K3/017
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A pulse-based flip flop circuit includes a pulse generator generating a pulse signal and an inverted pulse signal, a scan hold buffer holding a scan input signal for a delay time, and a latch circuit including an intermediate node receiving either a data signal or the scan input signal responsive to a scan enable signal, the pulse signal and the inverted pulse signal. The pulse generator circuit includes a direct path providing a clock signal as a direct path input to a NAND circuit; a delay path including a number of plural stages that delay the clock signal and provide a delayed clock signal as a delay path input to the NAND circuit that performs a NAND operation on the direct path and delay path inputs to generate the inverted pulse signal; and a feedback path providing the pulse signal to a first stage among the stages of the delay path.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.