Hardware-based packet flow processing
US11799785B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 31, 2021 |
| Grant date | Oct 24, 2023 |
| Priority date | — |
| Expiry date | May 31, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L45/586
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
Techniques are disclosed for processing data packets by a hardware-based networking device configured to disaggregate processing of data packets from hosts of a virtualized computing environment. The hardware-based networking device includes a hardware-based component implementing a plurality of behavioral models indicative of packet processing graphs for data flows in the virtualized computing environment. A data packet having a source from or destination to an endpoint in a virtual network of the virtualized computing environment is received. Based on determining that the data packet is a first packet of a data flow to or from the endpoint, one of the behavioral models is mapped to the data flow. The packet is modified in accordance with the mapped behavioral model. A state of the data flow is stored. Subsequent data packets of the data flow are processed based on the stored state.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.