Low-dropout (LDO) voltage regulator with voltage droop compensation circuit
US11803204B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 23, 2021 |
| Grant date | Oct 31, 2023 |
| Priority date | — |
| Expiry date | Jul 3, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04B1/40
- WIPO fieldControl
- WIPO sectorInstruments
Abstract
The disclosure relates to an apparatus including: a first set of one or more field effect transistors (FETs) coupled between a first voltage rail and a load; a second set of one or more FETs coupled between the first voltage rail and the load; a gate voltage control circuit configured to: provide a first set of gate voltages to first and second gates of the first and second sets of one or more FETs in accordance with a first mode of operation, respectively; and provide a second set of gate voltages to the first and second gates of the first and second sets of one or more FETs in accordance with a second mode of operation, respectively; and a voltage droop compensation circuit configured to control an output voltage across the load during a transition from the first mode of operation to the second mode of operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.