Deep learning algorithm compiling method, device, and related product
US11803404B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 25, 2020 |
| Grant date | Oct 31, 2023 |
| Priority date | — |
| Expiry date | Mar 1, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06N3/063
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present disclosure relates to a deep learning algorithm compiling method and a device and a related product, the product comprising a controller unit, and the controller unit comprising: an instruction cache unit, an instruction processing unit, and a queue-storing unit. The instruction cache unit is configured to store computation instructions associated with artificial neural network operations. The instruction processing unit is configured to parse the computation instructions to obtain a plurality of operation instructions. The queue-storing unit is configured to store an instruction queue, which comprises: a plurality of operation instructions or computation instructions to be executed according to the front-to-rear sequence of the queue. By means of the described method, the present disclosure may improve the operation efficiency of the related product when carrying out neural network model operations.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.