Parallel merge sorter circuit
US11803509B1 · kind B1 · utility
1Cited by
3References
20Claims
0Family size
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Key dates
| Filing date | May 23, 2022 |
| Grant date | Oct 31, 2023 |
| Priority date | — |
| Expiry date | May 23, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F15/8061
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A merge sort circuit can include a parallel merge sort core that performs a partial merge on two input tuples, each containing a number P of data elements sorted according to a sort key, to produce a sorted output tuple of P data elements. Input data blocks to be merged can be stored in first and second block buffers. The block buffers can receive data from a vector memory read interface that reads groups of at least P data elements at a time. Loading of data elements into the block buffers can be based on respective fill levels of the block buffers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.